Intel Unveils 18A Node With 25% Frequency Gain and 36% Power Savings Over Intel 3
RibbonFET and PowerVia technologies lead Intel’s next-gen 18A node to massive leaps in performance, power efficiency, and transistor density.
Intel 18A: Ushering a New Era in CMOS Design
At the 2025 Symposium on VLSI Technology and Circuits, Intel officially detailed its advanced 18A process node, positioning it as the direct successor to Intel 3. Designed to power future computing platforms like Panther Lake (client CPUs) and Clearwater Forest (Xeon E-Cores), 18A delivers significant gains across performance, power, and density metrics.
- The process features RibbonFET (GAA transistors) and PowerVia (backside power delivery), both critical enablers for advanced chip scaling.
- Intel states the node offers over 30% logic density improvements and an entire node’s worth of performance uplift compared to Intel 3.
Major Efficiency and Performance Gains
Intel 18A exhibits 25% higher frequency at the same voltage (ISO) and 36% lower power at identical frequency versus its predecessor.
- At 1.1V, 18A can clock up to 25% faster than Intel 3.
- When operating below 0.65V, the same frequency performance results in up to 38% power savings.
These advancements stem from innovations in transistor structure, power delivery, and interconnect design.
RibbonFET & PowerVia: Key Drivers of Progress
RibbonFET, Intel’s implementation of Gate-All-Around (GAA) transistors, replaces traditional FinFET with improvements in:
- Gate electrostatics for superior control,
- Higher effective width per footprint,
- Reduced parasitic capacitance and leakage.
The introduction of customizable ribbon widths across HP (180H) and HD (160H) libraries also allows enhanced tuning of performance vs. leakage. Additionally, SRAM optimization through specialized ribbons enhances both bitcell performance and area efficiency.
PowerVia, Intel’s backside power delivery solution, separates power and signal paths, resulting in:
- Improved logic density and standard cell utilization,
- Lower resistance-capacitance (RC) values,
- Dramatically reduced voltage droop, and
- Up to 10x improvement in IR drop tolerance.
Specifications and Library Scaling
Key Intel 18A specs include:
- Contacted Poly Pitch: 50nm
- Metal Pitch (M0): 32nm
- SRAM Cell Area: 0.0230µm² (HCC) / 0.0210µm² (HDC)
- Frontside Metal Layers: 10ML (low cost), 10ML (HD), 14-16ML (HP)
- Backside Metal Layers: 3ML + 3ML
The 18A node also introduces library height reductions for further scaling:
- HP Library: 180nm (vs. 240nm in Intel 3)
- HD Library: 160nm (vs. 210nm in Intel 3)
Future Iterations: 18A-P and 18A-PT Incoming
Intel plans to evolve this process further through variants 18A-P and 18A-PT, scheduled between 2026 and 2028. These will serve a broader set of customers in high-performance computing and AI workloads.
A Competitive Leap in Process Technology
With up to 39% density improvement, massive power savings, and substantial clock speed gains, Intel 18A is poised to compete fiercely with nodes from TSMC and Samsung. The integration of RibbonFET and PowerVia underscores Intel’s renewed focus on design-technology co-optimization, cementing its ambitions to regain process leadership in the AI era.
